Polynomial Model for Computing Noise Levels in Frequency Synthesisers

Authors: Kacharmina E.G., Tolkachev P.A., Shakhtarin B.I. Published: 16.04.2018
Published in issue: #2(119)/2018  
DOI: 10.18698/0236-3933-2018-2-41-47

Category: Instrument Engineering, Metrology, Information-Measuring Instruments and Systems | Chapter: Telecommunication Systems, Networks and Devices  
Keywords: polynomial Model for Computing Noise Levels in Frequency Synthesisers, frequency synthesiser, phase noise, phase-locked loop, polynomial model

The article describes principles of operation behind frequency synthesisers with fractional-N dividers. We analysed noise characteristics of all the elements the synthesisers comprise. We developed a polynomial model for computing noise levels in frequency synthesisers. We present the results of simulating phase noises by the polynomial method for all circuit elements, as well as a comparison of these results to simulation performed in the ADIsimPLL software package


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